Lower bounds on communication complexity
Information and Computation
Multi-level logic synthesis using communication complexity
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Computational Complexity of Controllability/Observability Problems for Combinational Circuits
IEEE Transactions on Computers
Matrix computations (3rd ed.)
Las Vegas is better than determinism in VLSI and distributed computing (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
The entropic limitations on VLSI computations(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
On Polynomial-Time Testable Combinational Circuits
IEEE Transactions on Computers
| Hi-index | 14.98 |
Considers polynomial time testability of combinational circuits generated by input decomposition, especially those generated by the logic synthesis tool FACTOR. First, the complexity of the fault detection problem in this class of circuits is explored using a stuck-at fault model. An O(2/sup k/m) algorithm for detecting a single stuck-at fault is given that is faster than the O(16/sup k/m), previously reported best algorithm proposed by Fujiwara(1990), where k is the number of inputs in a subcircuit and m the number of signal lines in the circuit. Efficient, polynomial time algorithms are described for generating a test set for all single stuck-at faults in the circuit. The basic strategy is to eliminate backtracks during line justification by constructing tables or vector sets in each subcircuit, which makes the fault propagation procedure very simple and eventually results in an efficient test generation procedure. This presentation of efficient polynomial time test generation algorithms for FACTOR-generated circuits is important, since it shows that it is possible to synthesize circuits that are optimized for area and are polynomial time testable at the same time.