Logic testing and design for testability
Logic testing and design for testability
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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Signature Based Test Generation continues to grow in importance as VLSI circuits cross and leap beyond the multi-million-gate mark. The Logic Built-In Self Test (LBIST) methodology is a signature analysis based test generation strategy in wide spread use today. Since the LBIST hardware forms the basis for the generation of test patterns and failure-mode diagnostics, it is paramount that the LBIST test structures conform to LBIST methodology requirements. If the LBIST structures are modeled incorrectly, then pattern mismatches may occur at the tester. This paper describes a set of production level algorithms and procedures used to validate the LBIST structures used in the LBIST methodology. The validation includes the identification and verification of individual components of the LBIST structure. These algorithms are based on the test structure validation processes designed within IBM's TestBench test generation system.