Logic testing and design for testability
Logic testing and design for testability
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On Test Pattern Compaction Using Random Pattern Fault Simulation
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we introduce a new measure for target fault selection and backtrace during test generation. The measure incorporates information on undetected faults and hence attempts to maximizethe number of additional faults that may be detected by each test vector.Experimental results show the usefulness of this heuristic and demonstrate its superiority over the use of the SCOAP measure.