Logic testing and design for testability
Logic testing and design for testability
VLSI design synthesis with testability
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Transistor-level test generation for physical failures in CMOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment
EURO-DAC '91 Proceedings of the conference on European design automation
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The authors present a method for fully testing chips designed using synthesis and silicon compilation. The method is targeted for a multiprocessor architecture that implements low-speed to medium-speed signal-processing algorithms. By taking advantage of the specific properties of the architecture, the method allows a chip to be partitioned into several functional units. The authors use the C-test concept instead of the traditional automatic test-pattern generation to derive a compact set of test vectors. The fault model covers both the stuck-at class and part of the transistor stuck-open and stuck-closed cases. For large units with embedded memory, the authors adopt a self-test approach.