Logic testing and design for testability
Logic testing and design for testability
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Verifying a Multiprocessor Cache Controller Using Random Test Generation
IEEE Design & Test
IEEE Design & Test
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Three well-known algorithms for the automatic test pattern generation (ATPG) for digital circuits are the D algorithm, Podem, and Fan. The author introduces the concept of test generation and analyzes the way each algorithm uses search and backtracking techniques to sensitize a fault and propagate it to an observable point. The heuristics used to guide ATPG search and the notation used to represent circuit values are examined.