High-Level Test Generation for VLSI

Authors:
Debashis Bhattacharya;Brian T. Murray;J. P. Hayes
Affiliations:
Yale Univ., New Haven, CT;General Motors Research Labs., Warwick, MI;Univ. of Michigan, Ann Arbor
Venue:
Computer
Year:
1989

Citing 5
Cited 1

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Abstract

The authors survey high-level approaches to test generation for VLSI circuits, which can significantly reduce test generation time while still providing good fault coverage. High-level approaches view the circuit with less structural detail, that is, from a more abstract viewpoint and often hierarchically. The authors first review some basic circuit and fault models and the two most widely known test-generation algorithms as a basis for comparison between high-level and low-level techniques. The authors then examine the more important high-level approaches, which fall into two broad classes, namely algorithmic and heuristic.