Logic testing and design for testability
Logic testing and design for testability
Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Partitioning circuits for inproved testability
Proceedings of the fourth MIT conference on Advanced research in VLSI
Artificial intelligence
Simulated annealing and combinatorial optimization
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatisierung des Entwurfs vollständig testbarer Schaltungen
GI - 18. Jahrestagung II, Vernetzte and komplexe Informatik-Systems
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
Test pattern generation hardware motivated by pseudo-exhaustive test techniques
EURO-DAC '94 Proceedings of the conference on European design automation
Logic partitioning to pseudo-exhaustive test for BIST design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
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In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, instead of path-sensitizing. The developed cells segment the entire circuits into exhaustively testable parts, and the presented algorithms place these cells, under the objective to minimize the hardware overhead.The approach is completely compatible with the usual LSSD-rules. The analysis of the well-known benchmark circuits shows only little additional hardware costs.