IEEE Transactions on Computers - Special issue on fault-tolerant computing
Tools and devices supporting the pseudo-exhaustive test
EURO-DAC '90 Proceedings of the conference on European design automation
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GLFSR-a new test pattern generator for built-in-self-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A fully scanned digital circuit can be tested pseudo-exhaustively by first introducing a number of extra bypass storage cells to limit the test-phase input dependency of each test-phase output and then using a Linear Feedback Shift Register (LFSR) to feed the chain of the original scan cells and the extra cells. For the design of the LFSR, the goal is to minimize the pseudo-exhaustive test length with low hardware overhead. If the LFSR uses a primitive characteristic polynomial then it requires only one seed, but the candidate primitive polynomials may all fail to satisfy the target test length. In this paper, we present a methodology that enlarges the list of candidate polynomials, if the prescribed number of seeds is more than one. Experimental results show that the new candidate polynomials are often instrumental in satisfying the given test length and seed restriction.