An efficient delay test generation system for combinational logic circuits

Authors:
Eun Sei Park;M. Ray Mercer
Affiliations:
Mentor Graphics Corporation, 8500 Creekside Place, Beaverton, OR;Department of ECE, The University of Texas at Austin, Austin, TX
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

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Abstract

This paper presents an efficient delay test generation system for combinational logic circuits. Delay testing problems are divided into gross delay fault testing and small delay fault testing in order to explore the trade-off between the levels of delay testing effort and the confidence levels of proper system operation. Complete automatic test pattern generation algorithms are proposed for both gross delay faults and small delay faults. Especially for the small delay fault test generation, new search space enumeration techniques are employed so as to bias the search space such that a delay test for relatively long paths can be found. Also a novel timing analysis method via functionality check is presented for delay test generation. Finally, complete test results are demonstrated for both gross delay faults and small delay faults on several benchmark circuits.