Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling

Authors:
Hyungwon Kim;John P. Hayes
Affiliations:
-;-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

Citing 17
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Abstract

Delay testing of designs that contain intellectual property(IP) cores is challenging. We propose a method that can testpaths traversing both IP cores and user-defined blocks. Itemploys a highly efficient BDD-based path modeling methodand an associated ATPG technique. Experimental resultsshow that it robustly tests selected paths without using extralogic, and, at the same time, protects the intellectual property.