Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Error-Resilient Test Data Compression Using Tunstall Codes
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Evaluation of Error-Resilience for Reliable Compression of Test Data
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel methodology to improve error resilience for reliable compression of test data of VLSI circuits. The presence of so-called "bit-flips" (due to the high speed manufacturing test or noise in the Automatic Test Equipment (ATE) head) can lead to a significant loss in coverage when compression is employed. As reported in the technical literature, coverage can experience a reduction of as much as 30% due to bit-flips in the compressed sequence of the test data. Differently from reported works, the proposed technique adds a very small amount of redundant information to test data prior to its compression; the objective of the redundant data is to limit the so-called "propagation" effect due to bit-flips once the sequence is decompressed. Extensive simulation results are presented to substantiate the increase in error resilience and to evaluate the impact of the redundancy introduced by the proposed approach on the compression ratio. It is shown that for the ISCAS89 benchmark circuits the reduction in coverage is only 0.20%-3.52% which is significantly better than previously reported works.