Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Configuration Compression for Virtex FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Dynamic Reconfiguration Optimisation with Streaming Data Decompression
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Decoding-aware compression of FPGA bitstreams
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bitmask-Based Code Compression for Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
In this paper we propose an optimized bitstream compression algorithm based on LZ and a novel architecture of decompressor, the proposed algorithm improves the Compression Ratio by fully utilizing the regularity of configuration bits of CLB (Configurable Logic Box) in FPGA and using the variable length Golomb coding method. The experimental results show that the Optimized method can improve the Compression Ratio of LZSS by 32.3% for bitstream with high regularity and 10.3% for bitstream with low regularity, and our approach shows a higher flexibility than the BMC+RLE arithmetic when compressing the bitstream with high regularity for various FPGA. Moreover, we design a two-buffer-window decompressor to download the compressed bitstreams. In order to increase the throughput of the proposed decompressor, we design a multi-stage data selector in it. The post-simulation of the decompressor shows that its throughput is up to 9280 Mbps under 65nm CMOS process. And that is 4352Mbps when verified on a Virtex-5 FPGA.