Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Testing the 400-MHz IBM Generation-4 CMOS Chip
Proceedings of the IEEE International Test Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Processor Description Languages
Processor Description Languages
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Software based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper we propose an efficient methodology for processor core self-testing based on the knowledge of its instruction set architecture and register transfer level description and we demonstrate it on a processor core benchmark. We also demonstrate that our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while the same fault coverage is achieved with an order of magnitude smaller test application time compared with a recently published structural methodology for processor core self-testing.