A hardware architecture for subtractive clustering

Authors:
Marcos Santana Farias;Nadia Nedjah;Luiza De Macedo Mourelle
Affiliations:
Rua Helio de Almeida, 75, Cidade Universitaria – Ilha do Fundao, Rio de Janeiro, RJ, CEP: 21941-906, Brazil.;Rua Sao Francisco Xavier, 524, Sala 5145-F, Maracana, Rio de Janeiro, RJ, CEP: 20550-900, Brazil.;Rua Sao Francisco Xavier, 524, Sala 5145-F, Maracana, Rio de Janeiro, RJ, CEP: 20550-900, Brazil
Venue:
International Journal of High Performance Systems Architecture
Year:
2011

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Abstract

Clustering algorithms are used extensively to organise and categorise abundant data. This paper describes the implementation of subtractive clustering algorithm in hardware. The solution developed in this paper seeks a hardware implementation to automatic and fast identification of cluster centres. This hardware proposed is generic so it can be used in any data classification problems, omnipresent in identification systems.