Functional test-sequence grading at register-transfer level

Authors:
Hongxia Fang;Krishnendu Chakrabarty;Abhijit Jas;Srinivas Patil;Chandra Tirumurti
Affiliations:
Department of Electrical and Computer Engineering, Duke University, Durham, NC;Department of Electrical and Computer Engineering, Duke University, Durham, NC;Intel Corporation, Austin, TX;Intel Corporation, Austin, TX;Intel Corporation, Austin, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

We propose output deviations as a surrogate metric to grade functional test sequences at the register-transfer level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the Scheduler module of the Illinois Verilog Model show that the deviations metric is computationally efficient and it correlates well with gate-level coverage for stuck-at, transition-delay and bridging faults. Results also show that functional test sequences reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods.