Genetic Algorithms Plus Data Structures Equals Evolution Programs
Genetic Algorithms Plus Data Structures Equals Evolution Programs
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Template for Scatter Search and Path Relinking
AE '97 Selected Papers from the Third European Conference on Artificial Evolution
Parallelization of the scatter search for the p-median problem
Parallel Computing - Special issue: Parallel computing in logistics
Scatter Search: Methodology and Implementations in C
Scatter Search: Methodology and Implementations in C
Parallel Metaheuristics: A New Class of Algorithms
Parallel Metaheuristics: A New Class of Algorithms
A hardware Memetic accelerator for VLSI circuit partitioning
Computers and Electrical Engineering
Practical fpga programming in c
Practical fpga programming in c
The Verilog Hardware Description Language
The Verilog Hardware Description Language
Implementation of a genetic algorithm on a virtex-ii pro FPGA
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Parallel FPGA-based implementation of scatter search
Proceedings of the 12th annual conference on Genetic and evolutionary computation
Unleash the System On Chip using FPGAs and Handel C
Unleash the System On Chip using FPGAs and Handel C
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Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard optimization problems. However, the time required to find high-quality solutions can become prohibitive as problem sizes grow. In this paper, we present a hardware implementation of Scatter Search on a field-programmable gate array (FPGA). Our objective is to improve the run time of Scatter Search by exploiting the potentially massive performance benefits that are available through the native parallelism in hardware. When implementing Scatter Search we employ two different high-level languages (HLLs): Handel-C and Impulse-C. Our empirical results show that by effectively exploiting source-code optimizations, data parallelism, and pipelining, a 28x speed up over software can be achieved.