Automata-Based Symbolic Scheduling for Looping DFGs
IEEE Transactions on Computers
A low-power content-adaptive texture mapping architecture for real-time 3D graphics
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
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This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. This paper proposes a methodology, called TCLP, based on dividing the problem into two simpler and independent tasks: retiming and scheduling. TCLP explores different sets of resources, searching for a maximum resource utilization. This reduces area requirements. After a minimum set of resources has been found, the execution throughput is increased and the number of registers required by the loop schedule is reduced. TCLP attempts to generate a schedule which minimizes cost in time and area (resources and registers). The results show that TCLP obtains optimal schedules in most cases.