Redundancies and don't cares in sequential logic synthesis
Journal of Electronic Testing: Theory and Applications
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An Automaton Model for Scheduling Constraints in Synchronous Machines
IEEE Transactions on Computers
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
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Previous work in automata theory has shown how to eliminate sequential redundancy from networks of FSMs by finding sequences of inputs and outputs which are never communicated between components of the network. This paper shows that behavior automata—finite-state machines whose inputs and outputs are incompletely scheduled—exhibit similar properties. Using the behavior FSM (BFSM) as a model for scheduling, we show how to identify and eliminate both input and output scheduling don‘t-cares. When a scheduling don‘t-care is eliminated from a network of BFSMs, the register-transfer implementation is guaranteed not to suffer from the corresponding don‘t-care sequence. A definition of scheduling don‘t-cares improves our understanding of the foundations of high-level synthesis and the relationship between high-level and sequential optimization. In practice, scheduling don‘t-care elimination is a powerful tool for eliminating redundancy early in the design process.