A transformational approach to register-transfer-level design-space exploration
A transformational approach to register-transfer-level design-space exploration
Behavior-preserving transformations for high-level synthesis
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
A general methodology for synthesis and verification of register-transfer designs
DAC '84 Proceedings of the 21st Design Automation Conference
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The paper investigates the problem of designing high level synthesizers which would guarantee correctness of the designs produced. No satisfactory solution to this problem had been available so far. The paper presents a formal framework in which the synthesis and verification processes can be modelled in a practical way. It is shown that the complexity of the verification process can be reduced by following the modularity usually present in a synthesizer design. To simplify the correctness proof of the individual synthesis steps, some easily verifiable templates are defined, in which the algorithms can be expressed. The methodology is embedded in HOL (Higher Order Logic) system.