Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
The design of the UNIX operating system
The design of the UNIX operating system
MC68851: paged memory management unit user's manual
MC68851: paged memory management unit user's manual
Operating systems: concepts and design
Operating systems: concepts and design
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
MIPS RISC architecture
Performance of the VAX-11/780 translation buffer: simulation and measurement
ACM Transactions on Computer Systems (TOCS)
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Design tradeoffs for software-managed TLBs
ACM Transactions on Computer Systems (TOCS)
Surpassing the TLB performance of superpages with less operating system support
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
A new page table for 64-bit address spaces
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
Boosting superpage utilization with the shadow memory and the partial-subblock TLB
Proceedings of the 14th international conference on Supercomputing
Virtual memory on data diffusion architectures
Parallel Computing
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This tutorial describes the current crop of commercial memory management units (MMUs) for 32-bit microprocessors. The discussion includes both complex- and reduced-instruction-set computers (CISCs and RISCs). The rationale, principles, and issues related to hardware support for memory management and virtual memory are reviewed. The design and features of high-end microprocessor MMUs are reviewed and compared with respect to a common set of criteria. Special attention is paid to Unix requirements and multiprocessor, multiple MMU considerations. The MMUs covered are Intel 80386, i486, and i860; Motorola's 68851 (MMU for the 68020), 68030, 68040, and 88200 (MMU for the 88000 series); the Fujitsu MB86920 (Sparc MMU); and the MIPS R2000/R3000.