MIPS RISC architecture
Automatic generation of invariants and intermediate assertions
Theoretical Computer Science - Special issue: principles and practice of constraint programming
Automatic Generation of Invariants in Processor Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Computing Abstractions of Infinite State Systems Compositionally and Automatically
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Powerful Techniques for the Automatic Generation of Invariants
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
PN-based formal modeling and verification for ASIP architecture
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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Existing formal verification methods do not handle systems that combine state machines and data paths very well. Model checking deals with finitestate machines efficiently, but model checking full designs is infeasible because of the large amount of state in the data path. Theorem-proving methods may be effective for verifying data path operations, but verifying the control requires finding and proving inductive invariants that characterize the reachable states of the system.We present a new approach to verification of systems that combine control FSMs and data path operations. Invariants are specified only for a small set of control states, called clean states, where the invariants are especially simple.We avoid the need to specify the invariants for the unclean states by symbolically simulating over all paths to find the possible next clean states.The set of all paths from one clean state to the next is represented by a regular expression, which is extracted from the control FSMs. The number of paths is infinite only if the regular expression contains stars. The method uses a heuristic to generalize the symbolic state to cover all of the paths of the starred expression. We have implemented a prototype tool for guiding an existing symbolic simulator and verification tool and used it successfully to prove properties of the Instruction Fetch Unit of TORCH, a superscalar microprocessor designed at Stanford. With much less effort, we were able to find all the bugs in the unit that were found earlier by manually strengthening the invariants.