Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Embedded Robustness IPs for Transient-Error-Free ICs
IEEE Design & Test
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Fault Tolerant ICs by Area-Optimized Error Correcting Codes
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
IBM S/390 parallel enterprise server G5 fault tolerance: a historical perspective
IBM Journal of Research and Development
Implementation of a power-aware dynamic fault tolerant mechanism on the Ubichip platform
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
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Fault tolerant design is a technique emerging in Integrated Circuits (ICs) to deal with the increasing error susceptibility (Soft Errors, Single Event Upsets, (SEUs)) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects, thereby increasing the yield and lowering the production cost in certain conditions. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques for SEUs) leads to a synergistic advantage under certain conditions: lower production costs because of a better yield. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular designs are presented as function of IC area, fault tolerant overhead and defect density.