Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices

  • Authors:

  • S. Baloch;T. Arslan;A. Stoica

  • Affiliations:

  • Institute for System Level Integration, Alba Centre, Alba Campus, Livingston, EH54 7EG, UK;University of Edinburgh, Kings Buildings, Edinburgh,EH9 3JL, UK;Jet Propulsion Laboratory, NASA, 4800 Oak Grove Drive Pasadena, CA

  • Venue:
  • ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
  • Year:
  • 2006

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Abstract

This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (Single Event Transients) induced errors that can result in data loss for reconfigurable architectures. The proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. The result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes.