Fault Injection Techniques and Tools for Embedded Systems
Fault Injection Techniques and Tools for Embedded Systems
A New Hybrid Fault Detection Technique for Systems-on-a-Chip
IEEE Transactions on Computers
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Fault-Tolerant Systems
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
Partitioned Embedded Architecture Based on Hypervisor: The XtratuM Approach
EDCC '10 Proceedings of the 2010 European Dependable Computing Conference
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
Qualification and relifing testing for space applications applied to the agilent G-Link components
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
Evaluating the efficiency of data-flow software-based techniques to detect SEEs in microprocessors
LATW '11 Proceedings of the 2011 12th Latin American Test Workshop
Survey of virtual machine research
Computer
DeSyRe: On-demand system reliability
Microprocessors & Microsystems
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Due to performance issues commercial off the shelf components are becoming more and more appealing in application fields where fault tolerant computing is mandatory. As a result, to cope with the intrinsic unreliability of such components against certain fault types like those induced by ionizing radiations, cost-effective fault tolerant architectures are needed. In this paper we present an in-depth experimental evaluation of a hybrid architecture to detect transient faults affecting microprocessors. The architecture leverages an hypervisor-based task-level redundancy scheme that operates in conjunction with a custom-developed hardware module. The experimental evaluation shows that our lightweight redundancy scheme is able to effectively cope with malicious faults as those affecting the pipeline of a RISC microprocessor.