The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
UltraSPARC: the next generation superscalar 64-bit SPARC
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
UltraSPARC: Compiling for Maximum Floating Point Performance
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
VIS Speeds New Media Processing
IEEE Micro
UltraSPARC: Compiling for Maximum Floating Point Performance
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
High-Level Synthesis with SIMD Units
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
MAPLE chip: a processing element for a static scheduling centric multiprocessor
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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UltraSPARC-II extends the family of Sun's 64-bit SPARC V9 microprocessors, building on the UltraSPARC-I pipeline and adding critical enhancements to boost data bandwidth, hide memory latency, and improve floating-point and multimedia performance. New external cache and interface options allow more flexibility in system implementations. This paper describes the motivation and implementation of UltraSPARC-II's enhancements.