MAPLE chip: a processing element for a static scheduling centric multiprocessor

Authors:
Kenta Yasufuku;Riku Ogawa;Keisuke Iwai;Hideharu Amano
Affiliations:
Keio University, Hiyoshi Yokohama, Japan;Keio University, Hiyoshi Yokohama, Japan;National Defense Academy, Hashirimizu Yokosuka, Japan;Keio University, Hiyoshi Yokohama, Japan
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

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Abstract

A custom processor called MAPLE which supports static scheduling by automatic parallelizing compilers is implemented and evaluated. MAPLE has a high performance floating point arithmetic unit and low latency data transfer mechanism for other MAPLE chips. The maximum operational frequency is 80MHz in simulation, and the operation on the prototype board with 23MHz clock is confirmed. It requires about 0.56W at 23MHz operation.