High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
A variable-precision square root implementation for field programmable gate arrays
The Journal of Supercomputing - Special issue on field programmable gate arrays
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
MPEG video decoding with the UltraSPARC visual instruction set
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
UltraSPARC-II: the advancement of ultracomputing
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
High Level Synthesis Of Multi-Precision Data Flow Graphs
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Fugue for MMX [parallel programming]
IEEE Computer Graphics and Applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Hi-index | 0.00 |
This paper presents novel techniques to integrate the use of Single Instruction Multiple Data (SIMD) functional units in a high-level synthesis (HLS) design methodology. SIMD functional units can be configured to operate in one or more SIMD modes, in which they process multiple sets of smaller bitwidth operands in parallel. Conceptually, the use of SIMD functional units en-ables HLS to (i) exploit parallelism to a higher degree without using additional resources, (ii) improve resource utilization by enabling hardware re-use at a fine-grained level, and (iii) improve energy efficiency for a given area and/or performance constraint.We illustrate the issues involved in performing high-level syn-thesis with SIMD functional units, and discuss how algorithms involved in a typical high-level synthesis flow can be enhanced to result in maximal performance and energy improvements. These techniques are not restricted to specific high-level synthesis tools/algorithms, and can be plugged into any generic high-level synthesis system. Experimental results indicate that, the use of SIMD units can improve performance by up to 1.9X (average of 1.57X), and simultaneously reduce energy consumption by up to 33.16% (average of 28.03%) compared to well-optimized conven-tional designs, with minimal area overheads (average of 2.18%). The performance improvements can be translated into additional energy savings, resulting in upto 66.26% (average of 55.88%) en-ergy reductions. Further, our experiments demonstrate that, the use of SIMD units in a HLS tool results in a shift in the entire area-delay- energy tradeoff envelope that can be obtained, to include de-sirable parts of the design space (i.e., higher quality designs) that were hitherto unreachable.