Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip

  • Authors:

  • H. Blume;H. T. Feldkaemper;T. G. Noll

  • Affiliations:

  • Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, 52062 Aachen, Germany;Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, 52062 Aachen, Germany;Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, 52062 Aachen, Germany

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2005

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Abstract

The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy, in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.