Performance Modelling with Deterministic and Stochostic Petri Nets
Performance Modelling with Deterministic and Stochostic Petri Nets
Modeling methodology for integrated simulation of embedded systems
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
Journal of VLSI Signal Processing Systems
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze on-chip communication. In order to demonstrate the suitability of this approach, the on-chip communication structure of two examples featuring typical system-on-chip (SoC) communication conflicts like competition for common communication resources have been studied. A state-of-the-art heterogeneous digital signal processor (DSP) and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.