EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A multiobjective optimization model for exploring multiprocessor mappings of process networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A software framework for efficient system-level performance evaluation of embedded systems
Proceedings of the 2003 ACM symposium on Applied computing
Translating affine nested-loop programs to process networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
Journal of VLSI Signal Processing Systems
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
An optimization methodology for memory allocation and task scheduling in socs via linear programming
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A mapping framework for guided design space exploration of heterogeneous MP-SoCs
Proceedings of the conference on Design, automation and test in Europe
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The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But to be able to take advantage of the benefits of these systems, new strategies are required how to map applications to such a system and how to evaluate the system's performance at a very early design stage. We will present a static, analytical, bottom-up methodology for temporal and spatial mapping of applications to MP-SoCs based on packing. Furthermore we will demonstrate how the result can be used for performance evaluation and system improvement without the need for simulations.