The IBM System/370 Vector Architecture: Design Considerations
IEEE Transactions on Computers
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Software metrics and microcode: a case study
Journal of Software Maintenance: Research and Practice
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
An Architectural Overview of the Programmable Multimedia Processor, TM-1
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
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It is well-known that the main disadvantages associated with reconfigurable hardware are long reconfiguration latencies, high opcode space requirements, and complex decoder hardware. To overcome these disadvantages, we use microcode since it allows emulation of"complex" operations which are performed using a sequence of smaller and simpler operations. Microcode is used to control the reconfiguration of the reconfigurable hardware, either online or off-line, and the execution on the reconfigurable hardware. Due to the multitude of microcodes and their sizes, it is not feasible to provide on-chip storage for all microcodes. Consequently, the loading of microcode into a limited on-chip storage facility is becoming increasingly more important. In this paper, we present two methods of loading microcodes into such an on-chip storage facility.