The TM3270 Media-Processor Data Cache

Authors:
Jan-Willem van de Waerdt;Stamatis Vassiliadis;Jean-Paul van Itegem;Hans van Antwerpen
Affiliations:
Philips Semiconductors, San Jose, CA, USA;Delft University of Technology Delft, The Netherlands;Philips Semiconductors, San Jose, CA, USA;Philips Semiconductors, San Jose, CA, USA
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "twoslot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.