General purpose parallel architectures
Handbook of theoretical computer science (vol. A)
Lower Bounds on Communication Loads and Optimal Placements in Torus Networks
IEEE Transactions on Computers
Efficient Two-Level Mesh based Simulation of PRAMs
ISPAN '96 Proceedings of the 1996 International Symposium on Parallel Architectures, Algorithms and Networks
Networks on chip
Address-free all-to-all routing in sparse torus
PaCT'07 Proceedings of the 9th international conference on Parallel Computing Technologies
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In the Network-On-Chip context, a number of computational units are connected to each other via a network. The computational units act as sources and sinks of messages that the units send to each other to implement some distributed computational functionality. When the units need to intensively send messages to each other, ordinary dense interconnection networks will not have enough bandwidth to transfer the messages at the same pace as those are produced by the computational units. We consider a sparse cube-connected-cycles network as a candidate for NOCs. Such a sparse network will have enough bandwidth to support high-throughput computing in the NOCs context. We show a grid-like layout for the sparse cube-connected-cycles network and give properties of such a layout. We compare the layout properties to previously reported properties of layouts for sparse mesh-based networks. Although the logical diameter of the sparse cube-connected-cycles network is favorable, its other properties are found to be rather poor.