Towards a first vertical prototyping of an extremely fine-grained parallel programming approach
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
PRAM-on-chip: first commitment to silicon
Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures
Fpga-based prototype of a pram-on-chip processor
Proceedings of the 5th conference on Computing frontiers
Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures
ISPA '12 Proceedings of the 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications
Multi-core Portability Abstraction
IPDPSW '12 Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
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We study benchmarking on modern chip multi-processors (CMP), and outline a set of programs to measure the architectural performance properties, focusing on the REPLICA architecture employing a hybrid of PRAM and NUMA computational models. We analyse the parallel data processing and storage mechanisms on mainstream and research CMPs and their utilization in benchmarks to identify the strong and weak points of REPLICA and to further develop the benchmarks to demonstrate its scalability and performance.