Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
IEEE Transactions on Computers
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
IEEE Micro
Error and Flow Control in Terabit Intelligent Optical Backplanes
Architektur von Rechensystemen, Systemarchitektur auf dem Weg ins 3. Jahrtausend: Neue Strukturen, Konzepte, Verfahren und Bewertungsmethoden - Vorträge der 15. GI/ITG-Fachtagung ARCS '99 und der APS'99 (Arbeitsplatzrechensysteme)
1 Gb/s VCSEL/CMOS Flip-Chip 2-D-Array Interconnects and Associated Diffractive Optics
PI '99 Proceedings of the The 6th International Conference on Parallel Interconnects
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
High-speed CMOS switch designs for free-space optoelectronic MIN's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable electronic packet switches
IEEE Journal on Selected Areas in Communications
Deficit round-robin scheduling for input-queued switches
IEEE Journal on Selected Areas in Communications
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Run-time reconfiguration of communication in SIMD architectures
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Optical packet switching: A reality check
Optical Switching and Networking
Hi-index | 0.01 |
The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both un-pipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-µm CMOS technology is illustrated. The pipelined switch design occupies 2 of CMOS area, and consumes