Randomized parallel communications on an extension of the omega network
Journal of the ACM (JACM)
A self-routing permutation network
Journal of Parallel and Distributed Computing
On-line algorithms for path selection in a nonblocking network
STOC '90 Proceedings of the twenty-second annual ACM symposium on Theory of computing
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Fast Self-Routing Permutation Switching on an Asymptotically Minimum Cost Network
IEEE Transactions on Computers
On the universality of multipath multistage interconnection networks
Interconnection networks for high-performance parallel computers
Randomized Routing with Shorter Paths
IEEE Transactions on Parallel and Distributed Systems
Parallel permutation and sorting algorithms and a new generalized connection network
Journal of the ACM (JACM)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Rearrangeable Three-Stage Interconnection Networks and Their Routing Properties
IEEE Transactions on Computers
An O(log2 N) Depth Asymptotically Nonblocking Self-Routing Permutation Network
IEEE Transactions on Computers
Universal schemes for parallel communication
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A bit-controlled multichannel time slot permutation network
MPPOI '95 Proceedings of the Second Workshop on Massively Parallel Processing Using Optical Interconnections
The ip–p Rearrangement and Failure-Tolerance of Double p-ary Multirings and Generalized Hypercubes
Automation and Remote Control
Power complexity of multiplexer-based optoelectronic crossbar switches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On tracking the behavior of an output-queued switch using an input-queued switch
IEEE/ACM Transactions on Networking (TON)
| Hi-index | 14.98 |
Principles for designing practical self-routing nonblocking N脳N circuit-switched connection networks with optimal 驴(N· log N) hardware at the bit-level of complexity are described. The overall principles behind the architecture can be described as "Expand-Route-Contract." A self-routing nonblocking network with w-bit wide datapaths can be achieved by expanding the datapaths to w + z independent bit-serial connections, routing these connections through self-routing networks with blocking, and by contracting the data at the output and recovering the w-bit wide datapaths. For an appropriate redundancy z, the blocking probability can be made arbitrarily small and the fault tolerance arbitrarily high. By using efficient space domain concentrators, the architecture yields self-routing nonblocking switching networks with an optimal O(N· log N) bits of memory or O(N· log N· log log log N) logic gates. By using a linear-cost time domain concentrator, the architecture yields self-routing nonblocking switching networks with an optimal 驴(N· log N) bits of memory or logic gates. These designs meet Shannon's lower bound on memory requirements, established in the 1950s. The number of stages of crossbars can match the theoretical minimum, which has not been achieved by previous self-routing networks. The architecture is feasible with existing electrical or optical technologies. The designs of electrical and optical switch cores with Terabits of bisection bandwidth for Networks-of-Workstations (NOWs) are described.