Maximization of power dissipation under random excitation for burn-in testing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Challenges and directions for testing IC
Integration, the VLSI Journal
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to "go after" the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.