SAT based ATPG using fast justification and propagation in the implication graph
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Challenges and directions for testing IC
Integration, the VLSI Journal
Checking equivalence of quantum circuits and states
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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We present a new algorithm for generating tests for single stuck line (SSL) faults in combinational logic circuits using a combination of Boolean and path-oriented techniques. We use Boolean techniques employing the ordered binary decision diagram (BDD) to limit the effect of hard faults on the performance of the algorithm. We use path-oriented techniques similar to those in conventional test generation algorithms to limit the number of algebraic operations that must be performed. The test set generated for each fault is exhaustive in the sense that we find all test patterns which make the fault observable at some primary output. We implemented the algorithm as the program TSUNAMI and applied it to the standard ISCAS '85 and ISCAS '89 benchmark circuits. Results indicate that for circuits which are amenable to analysis by BDD's, TSUNAMI performs significantly better than conventional algorithms such as FAN or EST in generating tests for all targeted faults. Moreover, TSUNAMI finds a large set of test vectors for each fault. The program can easily manipulate these sets of vectors to produce test vectors which test many faults. As a result, we are able to compress the sets of vectors into a very small total number of patterns