IEEE Transactions on Computers - Special issue on fault-tolerant computing
Codes, Curves, and Signals: Common Threads in Communications
Codes, Curves, and Signals: Common Threads in Communications
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
ATS '98 Proceedings of the 7th Asian Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Challenges and directions for testing IC
Integration, the VLSI Journal
On linear complexity of sequences over GF(2n)
Theoretical Computer Science
A new built-in TPG method for circuits with random pattern resistant faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this work, a new method to design a mixed-mode Test Pattern Generator (TPG) based only on a simple and single Linear Feedback Shift Register (LFSR) is described. Such an LFSR is synthesized by Berlekamp---Massey algorithm (BMA) and is capable of generating pre-computed deterministic test patterns which detect the hard-to-detect faults of the circuit. Moreover, the LFSR generates residual patterns which are sufficient to detect the remaining easy-to-detect faults. In this way, the BMA-designed LFSR is a mixed-mode TPG which achieves total fault coverage with short testing length and low hardware overhead compared with previous schemes according to the experimental results.