An efficient BIST design using LFSR-ROM architecture

Authors:
Lijian Li;Yinghua Min
Affiliations:
-;-
Venue:
ATS '00 Proceedings of the 9th Asian Test Symposium
Year:
2000

Citing 0
Cited 2

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set

IEEE Transactions on Computers
Scan-BIST based on transition probabilities

Proceedings of the 41st annual Design Automation Conference

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Abstract

Built-in self-test (BIST) is considered to be one of the most promising approaches to testing modern ICs. This paper proposes an efficient BIST design using LFSR-ROM architecture. It takes advantage of don't-care bits that remain during the process of test pattern generation. It determines the target fault set with an ATPG tool to achieve predefined fault coverage. It compresses the size of ROM in two dimensions to reduce the number of test patterns and ROM outputs as well. Experimental results demonstrate that the proposed scheme is able to reduce hardware overhead several-fold.