Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
HIST: a hierarchical self test methodology for chips, boards, and systems
Journal of Electronic Testing: Theory and Applications
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Finite fields
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Configuring Flip-Flops to BIST Registers
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
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A deterministic BIST scheme is presented whichrequires less hardware overhead than pseudo-randomBIST but obtains better or even complete fault coverageat the same time. It takes advantage of the fact thatany autonomous BIST scheme needs a BIST controlunit for indicating the completion of the self-test atleast.Hence, pattern counters and bit counters are alwaysavailable, and they provide information to beused for deterministic pattern generation by someadditional circuitry. This paper presents a systematicway for synthesizing a pattern generator which needsless area than a 32-bit LFSR for random pattern generationfor all the benchmark circuits.