Further results in polynomial addressing
IBM Journal of Research and Development
On optimization of storage hierarchies
IBM Journal of Research and Development
Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
Design of parallel fault-secure encoders for systematic cyclic block transmission codes
Microelectronics Journal
Hi-index | 14.98 |
A novel technique for address generation is presented in this correspondence. This scheme has two useful features. Addresses are generated with check bits as an integral part of the address in order to provide multi-fault-detection capability. To date, there exists no such scheme with this feature. Secondly, the addresses generated through this scheme are pseudorandom; therefore, they can be used for storage hierarchies using hash coding techniques.