Optimization of Memory Hierarchies in Multiprogrammed Systems
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
Program Modelling via Inter-Reference Gaps and Applications
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Memory Hierarchy Configuration Analysis
IEEE Transactions on Computers
Optimization of Memory Hierarchies in Multiprogrammed Computer Systems With Fixed Cost Constraint
IEEE Transactions on Computers
Store Address Generator with On-Line Fault-Detection Capability
IEEE Transactions on Computers
Delayed-Staging Hierarchy Optimization
IEEE Transactions on Computers
Determination of Cache's Capacity and its Matching Storage Hierarchy
IEEE Transactions on Computers
Entropy representation of memory access characteristics and cache performance
ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
ACM Transactions on Architecture and Code Optimization (TACO)
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A simple model of the storage hierarchies is formulated with the assumptions that the effect of the storage management strategy is characterized by the hit ratio fqnction. The hit ratio function and the device technology-cost function are assumed to be representable by power functions (or piece-wise power functions). The optimization of this model is a geometric programming problem. An explicit formula for the minimum hierarchy access time is derived; the capacity and technology of each storage level are determined. The opfimal number of storage levels in a hierarchy is shown to be directly proportional to the logarithm of the systems capacity with the constant of proportionality dependent upon the technolagy and hit ratio characteristics. The optimal cost ratio of adjacent storage levels is constant, as are the ratios of the device access times and storage capacities of the adjacent levels. An illustration of the effect of overhead cost and level-dependent cost, such as the cost per "box" and cos for managing memory faults is given and several generalizations are presented.