Using the inter- and intra-switch regularity in NoC switch testing
Proceedings of the conference on Design, automation and test in Europe
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Diagnosis of interconnect shorts in mesh NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Optimizing built-in pseudo-random self-testing for network-on-chip switches
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Structural Test and Diagnosis for Graceful Degradation of NoC Switches
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes.