A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects

Authors:
Ashok Narasimhan;Bhooma Srinivasaraghavan;Ramalingam Sridhar
Affiliations:
State University of New York at Buffalo;State University of New York at Buffalo;State University of New York at Buffalo
Venue:
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Year:
2006

Citing 0
Cited 2

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels

Proceedings of the Conference on Design, Automation and Test in Europe
A variation tolerant current-mode signaling scheme for on-chip interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Global interconnects pose a significant challenge to the dense Very Deep Submicron (VDSM) System-on-Chips (SoC), due to increasing wire delay and its variations. Hence, interconnection techniques which decrease delay, delay variation and ensure signal integrity, play an important role in future technologies. In this regard, current-mode low-swing interconnection techniques provide an attractive alternative to conventional full-swing voltage-mode techniques in terms of delay, power and noise immunity. In this paper, we present a new current-mode low swing interconnection technique that reduces the delay and delay variations in global interconnects. Simulation results indicate significant savings in power, reduction in delay and increase in noise immunity compared to other techniques.