Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Testing On-Die Process Variation in Nanometer VLSI
IEEE Design & Test
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
On-die sensors for measuring process and environmental variations in integrated circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Time-to-Digital Converters
Measurement-Based Ring Oscillator Variation Analysis
IEEE Design & Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an on-chip all-digital sensor architecture to capture process variation information. The proposed solution is based on the concept of variation amplification and uses the propagation delay measurement in a chain composed of series connected pass-transistors. The proposed sensor circuit is able to capture the local variation of nMOS and pMOS transistor individually. A sensor block is proposed, which contains N-type and P-type sensor circuit along with scan, control, and measurement circuitry. An array of sensor blocks with scan chain connection gathers process variation information all across the die. Detailed SPICE level simulations conducted for an industrial 45nm CMOS technology indicates its feasibility in sensing, and on-chip alldigital measurement of process variation effect.