Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Leakage-tolerant design techniques for high performance processors
Proceedings of the 2002 international symposium on Physical design
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 40th annual Design Automation Conference
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Topological Analysis for Leakage Prediction of Digital Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Maximum Leakage Power Estimation for CMOS Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Design Techniques for Gate-Leakage Reduction in CMOS Circuits
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Proceedings of the 2003 international symposium on Low power electronics and design
Average Leakage Current Estimation of CMOS Logic Circuits
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Leakage current of CMOS circuit increases dramatically with the technology scaling down and has become a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakages are considered three main determinants of total leakage current. Up to now, how to accurately estimate leakage current of large-scale circuits within endurable time remains unsolved, even though accurate leakage models have been widely discussed. In this paper, the authors first dip into the stack effect of CMOS technology and propose a new simple gate-level leakage current model. Then, a table-lookup based total leakage current simulator is built up according to the model. To validate the simulator, accurate leakage current is simulated at circuit level using popular simulator HSPICE for comparison. Some further studies such as maximum leakage current estimation, minimum leakage current generation and a high-level average leakage current macromodel are introduced in detail. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage current estimation methods are very accurate and efficient.