Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A sub-1V dual-threshold domino circuit using product-of-sum logic
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Synthesis of low-leakage PD-SOI circuits with body-biasing
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Reducing instruction cache energy consumption using a compiler-based strategy
ACM Transactions on Architecture and Code Optimization (TACO)
Leakage current estimation of CMOS circuit with stack effect
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Vector extraction for average total power estimation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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As supply voltage is scaled to below 1 V, leakage powerbecomes significant in CMOS ICs. This paper proposesnovel circuit techniques in PD-SOI technology to reducestandby power in the sub-1 V regime by over three ordersof magnitude while maintaining circuit speed and withminimal overhead. Simulation results obtained usingprocess parameters from an IBM 0.13 m PD-SOItechnology show considerable improvement overpreviously proposed methods as supply voltage is scaledto 0.5 V. A new design algorithm for efficientimplementation of these PD-SOI standby power reductionschemes is also described.