Reducing instruction cache energy consumption using a compiler-based strategy

Authors:
W. Zhang;J. S. Hu;V. Degalahal;M. Kandemir;N. Vijaykrishnan;M. J. Irwin
Affiliations:
Southern Illinois University, Carbondale, IL;The Pennsylvania State University, PA;The Pennsylvania State University, PA;The Pennsylvania State University, PA;The Pennsylvania State University, PA;The Pennsylvania State University, PA
Venue:
ACM Transactions on Architecture and Code Optimization (TACO)
Year:
2004

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Abstract

Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach.We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms. We also evaluate the sensitivity of these optimizations to different high-level compiler transformations, energy parameters, and soft errors.