Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Energy-Efficient Design of the Reorder Buffer
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
AMULET3: A High-Performance Self-Timed ARM Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Reducing instruction cache energy consumption using a compiler-based strategy
ACM Transactions on Architecture and Code Optimization (TACO)
Complexity-Effective Reorder Buffer Designs for Superscalar Processors
IEEE Transactions on Computers
Isolating Short-Lived Operands for Energy Reduction
IEEE Transactions on Computers
Power-aware compilation for register file energy reduction
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Late Allocation and Early Release of Physical Registers
IEEE Transactions on Computers
Exploiting register-usage for saving register-file energy in embedded processors
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Saving register-file static power by monitoring instruction sequence in ROB
Journal of Systems Architecture: the EUROMICRO Journal
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Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low power-consumption, but also high computing performance. To enhance performance while hold energy constraints, some high-end embedded processors, therefore, adopt conventional features to exploit instruction-level parallelism and increase clock rates. The reorder buffer (ROB) and the register file are the two most critical components to implement these features. The cooperation of them, however, causes serious leakage power, especially for a large register file. In this paper, we propose a pure hardware approach to reduce the leakage power for the register file, such that more complex features (e.g., out-of-order execution, speculation execution, etc) can be applied to high-end embedded processors. In the proposed approach, we design a monitoring scheme in the pipeline datapath to identify the timing of powering up or powering down a register. Simulation results show that our approach saves at least 50% power consumption of the register file, with almost negligible performance lost.